The pipelined analog-to-digital converter (ADC) is a popular architecture for converting analog signals to digital signals at resolutions of 8-14 bits and conversion speeds ranging from 1-5000 Mega-samples per second (MS/s), for example. Typical applications include digital receivers, base stations, digital imaging and video, and ultrasound.
Among the critical building blocks in the pipelined ADC is the multiplying digital-to-analog converter (MDAC), which interfaces successive converter stages in the pipeline. In the conventional implementation, the core of the MDAC is constructed using switched capacitor technology formed around a class-A transconductance amplifier. The charge transfer from the power supply to the capacitive load of the transconductance amplifier in this conventional MDAC is inherently inefficient because the amplifier draws a constant current, while it delivers on average only a small fraction of this current to the load. This inefficiency negatively effects the power consumption and/or bandwidth of the pipelined ADC.
The embodiments of the present disclosure will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.